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document number: mc33981 rev. 6.0, 5/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. single high-side switch (4.0 m ? ), pwm clock up to 60khz the 33981 is a high-frequency, self-protected 4.0 m ? r ds(on) high- side switch used to replace el ectromechanical relays, fuses, and discrete devices in power management applications. the 33981 can be controlled by pulse-width modulation (pwm) with a frequency up to 60 khz. it is designed for harsh environments, and it includes self-recovery features. t he 33981 is suitable for loads with high in-rush current, as well as motors and all types of resistive and inductive loads. the 33981 is packaged in a 12 x 12 non-leaded power-enhanced power qfn package with exposed tabs. features ? single 4.0 m ? r ds(on) maximum high-side switch ? pwm capability up to 60 khz with duty cycle from 5% to 100% ? very low standby current ? slew rate control with external capacitor ? overcurrent and overtemperature protection, undervoltage shutdown and fault reporting ? reverse battery protection ? gate drive signal for external low-side n-channel mosfet with protection features ? output current monitoring ? temperature feedback ? pb-free packaging designated by suffix code pna figure 1. 33981 simplified application diagram high-side switch 33981B ordering information device temperature range (t a ) package mc33981Bpna/r2 - 40c to 125c 16 pqfn scale 1:1 bottom view pna (pb-free suffix) 98arl10521d 16-pin pqfn (12 x 12) v dd i/o i/o i/o i/o a/d a/d mcu conf fs inls en inhs temp csns ocls sr gnd vpwr cboot out dls gls v dd m v pwr 33981
analog integrated circuit device data 2 freescale semiconductor 33981 internal block diagram internal block diagram figure 2. 33981 simplifi ed internal block diagram gnd out current recopy logic gate driver out csns vpwr en inhs inls cboot bootstrap supply slew rate control sr low-side gate driver gls undervoltage fs conf cross- conduction dls and protection temp temperature feedback ocls current protection overtemperature detection 5.0 v i conf i ocls i dwn r dwn 5.0 v detection
analog integrated circuit device data freescale semiconductor 3 33981 pin connections pin connections figure 3. pin connections table 1. pin definitions descriptions of the pins listed in the table below can be found in the functional description section located on page 12 . pin number pin name pin function formal name definition 1 csns reports output current monitoring this pin is used to generate a ground-referenced voltage for the microcontroller (mcu) to monitor output current. 2 temp reports temperature feedback this pin is used by the mcu to monitor board temperature. 3en input enable (active high) this pin is used to place the dev ice in a low-current sleep mode. 4 inhs input serial input high side this input pin is used to control the output of the device. 5fs reports fault status (active low) this pin monitors fault c onditions and is active low. 6 inls input serial input low side this pin is used to control an ex ternal low-side n-channel mosfet. 7 conf input configuration input this input manages mosfet n-channel cross-conduction. 8 ocls input low-side overload this pin sets the v ds protection level of the external low-side mosfet. 9 dls input drain low side this pin is the drain of the ex ternal low-side n-channel mosfet. 10 gls output low-side gate this output pin drives the gate of the external low-side n-channel mosfet. 11 sr input slew rate control this pin controls the output slew rate. 12 cboot input bootstrap capacitor this pin provides the high-pulse current to drive the device. 13 gnd ground ground this is the ground pin of the device. 14 vpwr input positive power supply this pin is the source input of operational power for the device. 15, 16 out output output these pins provide a protected high-side power output to the load connected to the device. 1 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 package transparent top view out out csns temp en inhs fs inls conf ocls dls gls sr cboot gnd vpwr
analog integrated circuit device data 4 freescale semiconductor 33981 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings power supply voltage steady-state v pwr -16 to 41 v input/output pins voltage (1) inhs, inls, conf, csns, fs , temp, en - 0.3 to 7.0 v output voltage positive negative v out 41.0 -5.0 v continuous output current (2) i out 40.0 a csns input clamp current i cl(csns) 15.0 ma en input clamp current i cl( en) 2.5 ma sr voltage v sr - 0.3 to 54.0 v c boot voltage c boot - 0.3 to 54.0 v ocls voltage v ocls - 5.0 to 7.0 v low-side gate voltage v gls - 0.3 to 15.0 v low-side drain voltage v dls - 5.0 to 41.0 v esd voltage (3) human body model (hbm) charge device model (cdm) corner pins (1, 12, 15, 16) all other pins (2-11, 13-14) v esd 2000 750 500 v thermal ratings operating temperature ambient junction ta tj - 40 to 125 - 40 to 150 c storage temperature t stg - 55 to 150 c thermal resistance (4) junction to power die case junction to ambient r jc r ja 1.0 20.0 c/w peak pin reflow temperature during solder mounting (5) t solder 245 c notes 1. exceeding voltage limits on inhs, inls, conf, csns, fs , temp, and en pins may cause a malfunction or permanent damage to the device. 2. continuous high-side output rating as long as maximum junction temperature is not ex ceeded. calculation of maximum output cur rent using package thermal resistance is required. 3. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ) and the charge device model (cdm), robotic (c zap = 4.0 pf). 4. device mounted on a 2s2p test board per jedec jesd51-2. 5. pin soldering temperature limit is for 10 seconds maximum durat ion. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device.
analog integrated circuit device data freescale semiconductor 5 33981 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electrical characteristics characteristics noted under conditions 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input (vpwr) battery supply voltage range fully operational extended (6) v pwr 6.0 4.5 ? ? 27.0 27.0 v v pwr supply current inhs = 1 and out open inls = 0 i pwr(on) ? 10.0 12.0 ma v pwr supply current inhs = inls = 0, en = 5.0 v, out connected to gnd i pwr(sby) ? 10.0 12.0 ma sleep state supply current (v pwr < 14 v, en = 0 v, out connected to gnd) t a = 25 c t a = 125 c i pwr(sleep) ? ? ? ? 5.0 50.0 a undervoltage shutdown v pwr(uv) 2.0 4.0 4.5 v undervoltage hysteresis v pwr(uvhys) 0.05 0.15 0.3 v power output (iout, vpwr) output drain-to-source on resistance ( i out = 20 a, t a = 25 c) v pwr = 6.0 v v pwr = 9.0 v v pwr = 13.0 v r ds(on)25 ? ? ? ? ? ? 6.0 5.0 4.0 m ? output drain-to-source on resistance (i out = 20 a, t a = 150 c) v pwr = 6.0 v v pwr = 9.0 v v pwr = 13.0 v r ds(on)150 ? ? ? ? ? ? 10.2 8.5 6.8 m ? output source-to-drain on resistance ( i out = -20 a, t a = 25 c) (7) v pwr = - 12 v r sd(on) ??8.0 m ? output overcurrent detection level 9.0 v < v pwr < 16 v i och 75 100 125 a current sense ratio 9.0 v < v pwr < 16 v, csns < 4.5 v c sr ? 1/20000 ? ? current sense ratio (c sr ) accuracy 9.0 v < v pwr < 16 v, csns < 4.5 v output current 5.0 a 15 a, 20 a and 30 a c sr_acc -20 -15 ? ? 20 15 % current sense voltage clamp i csns = 15 ma v cl(csns) 4.5 6.0 7.0 v notes 6. out can be commanded fully on, pwm is avai lable at room. low side gate driver is available. protections and diagnosis are not available. min/max parameters are not guaranteed. 7. source-drain on resistance (reverse drain-to -source on resistance) with negative polarity v pwr .
analog integrated circuit device data 6 freescale semiconductor 33981 electrical characteristics static electrical characteristics power output (vpwr) (continued) overtemperature shutdown t sd 160 175 190 c overtemperature shutdown hysteresis (8) t sdhys 5.0 ? 20 c low side gate driver (vpwr, vgls, vocls) low-side gate voltage v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v v pwr = 27 v v gls 5.0 8.0 12.0 12.0 5.4 8.4 12.4 12.4 6.0 9.0 13.0 13.0 v low-side gate sinked current v gls = 2 v, v pwr = 13 v i glsneg ? 100 ? ma low-side gate sourced current v gls = 2 v, v pwr = 13 v i glspos ? 100 ? ma low-side overload detection level versus low-side drain voltage v ocls - v dls , (v ocls 4.0 ?) v ds_ls -50 ? +50 mv control interface (conf, inhs, inls, en, ocls) input logic high voltage (conf, inhs, inls) v ih 3.3 ? ? v input logic low voltage (conf, inhs, inls) v il ? ? 1.0 v input logic voltage hysteresis (conf, inhs, inls) v inhys 100 600 1200 mv input logic active pulldown current (inhs, inls) i dwn 5.0 10 20 a enable pull-down resistor (en ) r dwn 100 200 400 k ? enable voltage threshold (en ) v en 2.5 v input clamp voltage (en ) i en < 2.5 ma v clen 7.0 ? 14 v input forward voltage (en ) v f(en) -2.0?-0.3v input active pullup current (ocls ) i ocls p 50 100 200 a input active pullup current (conf) i conf 5.0 10 20 a fs tri-state capacitance (8) c fs ? ? 20 pf fs low-state output voltage i fs = -1.6 ma v fsl ?0.20.4 v temperature feedback t a = 25c for v pwr = 14 v v tfeed 3.35 3.45 3.55 v temperature feedback derating (8) dt feed -8.5 -8.9 -9.3 mv/c notes 8. parameter is guaranteed by process monitoring but is not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect the approxim ate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33981 dynamic electrical characteristics static electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics characteristics noted under conditions 6.0 v v pwr 27 v, -40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit control interface and power output timing (cboot, vpwr) charge blanking time (cboot) (10) t on 10 25 50 s output rising slew rate v pwr = 13 v, from 10% to 90% of v out, sr capacitor = 4.7 nf, r l = 5.0 ? sr r 8.0 16 35 v/ s output falling slew rate v pwr = 13 v, from 90% to 10% of v out, sr capacitor = 4.7 nf, r l = 5.0 ? sr f 8.0 16 35 v/ s output turn-on delay time (11) v pwr = 13 v, sr capacitor = 4.7 nf t dlyon 200 400 700 ns output turn-off delay time (12) v pwr = 13 v, sr capacitor = 4.7 nf t dlyoff 500 1000 1500 ns input switching frequency (9) f pwm ? 20 60 khz output pwm ratio @ 60khz (13) r pwm 5.0 95 % time to reset fault diagnosis (over load on high side or external low side) t rstdiag 100 200 400 s output over current detection time t och 1.0 10 20 s notes 9. the mc33981 can work down (~100hz). the fault management re set can not be guaranteed with pwm frequency lower than 5khz (inhs=0 during 200us typ) 10. values for cboot=100nf. refer to the paragraph entitled sleep mode on page 13 . parameter is guaranteed by design and not production tested. 11. turn-on delay time measured from rising edge of inhs that turns the output on to v out = 0.5 v with r l = 5.0 ? resistive load. 12. turn-off delay time measured from falling edge of inhs that turns the output off to v out = v pwr -0.5 v with r l = 5.0 ? resistive load. 13. the ratio is measured at v out = 50% v pwr without sr capacitor. the device is capable of 100% duty cycle.
analog integrated circuit device data 8 freescale semiconductor 33981 timing diagrams static electrical characteristics timing diagrams figure 4. time delays functional diagrams figure 5. normal mode, cross-conduction management 0.5 v v pwr - 0.5 v vout inhs t dly(on) t dly(off) 0.0 v 5.0 v vout 90% vout 10% vout sr f sr r 50%v pwr r pwm en inhs inls out gls fs t on after conf 5.0 v
analog integrated circuit device data freescale semiconductor 9 33981 timing diagrams static electrical characteristics figure 6. normal mode, independent high side and low side en inhs inls out gls fs high side on high side off t on after conf 0.0 v
analog integrated circuit device data 10 freescale semiconductor 33981 electrical performance curves static electrical characteristics electrical performance curves figure 7. typical r ds(on) vs. temperature at v pwr = 13 v figure 8. typical sleep state supply current vs. v pwr at 150c figure 9. v out rise time vs. sr capacitor from 10% to 90% of v out at 25c and v pwr = 13 v 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 -50 0 50 100 150 200 temperature (c) rdson (mohm) r ds(on) (m ? ) temperature (c) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 4.5 6.0 9.0 12.0 12.5 13.0 14.0 17.0 21.0 vpwr(v) ipwr(sleep)(a) v pwr (v) i pwr(sleep) ( a) 1600 1400 400 1200 1000 800 600 200 0 0 2.0 4.0 6.0 8.0 10 sr capacitor (nf) vout rise time (ns)
analog integrated circuit device data freescale semiconductor 11 33981 electrical performance curves static electrical characteristics electrical performance curves figure 10. v out fall time vs. sr capacitor from 10% to 90% of v out at 25c and v pwr = 13 v 0 200 400 600 800 1000 1200 1400 1600 vout fall time (ns) 0 2.0 4.0 6.0 8.0 10 sr capacitor (nf)
analog integrated circuit device data 12 freescale semiconductor 33981 functional description introduction functional description introduction the 33981 is a high-frequency self-protected silicon 4.0 m ? r ds(on) high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. the 33981 can be controlled by pulse-width modulation (pwm) with a frequency up to 60 khz. it is designed for harsh environments, and it includes self-recovery features. the 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. a dedicated parallel input is available for an external low-side control with protection features and cross-conduction management. functional pin descriptions output current monitoring (csns) this pin is used to output a cu rrent proportional to the high- side out current and is used externally to generate a ground-referenced voltage for the microcontroller (mcu) to monitor out current. temperature feedback (temp) this pin reports an analog value proportional to the temperature of the gnd flag (pin 13). it is used by the mcu to monitor board temperature. enable [active high] (en) this is an input used to place the device in a low current sleep mode. this pin has an active passive internal pulldown. input high side (inhs) the input pin is used to directly control the out. this input has an active internal pulldown current source and requires cmos logic levels. fault status (fs ) this pin is an open drain-co nfigured output requiring an external pullup resistor to v dd (5.0 v) for fault reporting. when a device fault condition is detected, this pin is active low. input low side (inls) this input pin is used to directly control an external low- side n-channel mosfet and has an active internal pulldown current source and requires cmos logic levels. it can be controlled independently of the inhs depending of conf pin. configuration input (conf) this input pin is used to manage the cross-conduction between the internal high-side n-channel mosfet and the external low-side n-channel mosfet. the pin has an active internal pullup current source. when conf is at 0 v, the two mosfets are controlled independently. when conf is at v dd 5.0 v, the two mosfets cannot be on at the same time. low-side overload (ocls ) this pin sets the v ds protection level of the external low- side mosfet. this pin has an active internal pullup current source. it must be connect ed to an external resistor. drain low side (dls) this pin is the drain of the external low-side n-channel mosfet. its monitoring allows protection features: low side short protection and v pwr short protection. low-side gate (gls) this pin is an output used to drive the gate of the external low-side n-channel mosfet. slew rate control (sr) a capacitor connected between this pin and ground is used to control the output slew rate. bootstrap capacitor (cboot) a capacitor connected between this pin and out is used to switch the out in pwm mode. ground (gnd) this pin is the ground for the logic and analog circuitry of the device. positive power supply (vpwr) this pin connects to the positive power supply and is the source input of operational power for the device. the v pwr pin is a backside surface mount tab of the package. output (out) protected high-side power output to the load. output pins must be connected in parallel for operation.
analog integrated circuit device data freescale semiconductor 13 33981 functional device operation operational modes functional device operation operational modes the 33981 has 2 operating modes: sleep and normal depending on en input. sleep mode sleep mode is the state of the 33981 when the en is logic [0]. in this mode, out, the gate driver for the external mosfet, and all unused internal circuitry are off to minimize current draw. normal mode the 33981 will go to the normal operating mode when the en pin is logic [1]. the inhs and inls commands will be disabled t on after the en transitions to logic [1] to enable the charge of the bootstrap capacitor. protection and diagnostic features undervoltage the 33981 incorporates undervoltage protection. in case of v pwr < v pwr (uv) , the out is switched off until the power supply rises to v pwr (uv) + v pwr (uvhys) . the latched fault are reset below v pwr (uv) . overtemperature fault the 33981 incorporates over temperature detection and shutdown circuitry on out. ov ertemperature detection also protects the low-side gate driv er (gls pin). overtemperature detection occurs when out is in the on or off state and gls is at high or low level. for out, an over temperature fault condition results in out turning off until the temperature falls below t sd . this cycle will continue indefinitely until the offending load is removed. figure 12, page 16 and figure 18, page 20 show an over temperature on out. an over temperature fault on the low-side gate drive results in out turning off and the gls going to 0 v until the temperature falls below t sd . this cycle will c ontinue un til the offending load is removed. fs pin transition to logic [1] will be disabled typically t on after to enable the charge of the bootstrap capacitor. overtemperature faults force the temp pin to 0 v. overcurrent fault on high side the out pin has an overcurrent high-detection level called i och for maximum device protection. if at any time the current reaches this level, out will stay off and the csns pin will go to 0 v. the out pin is reset (and the fault is delatched) by a logic [0] at the inhs pin for at least t rst(diag) . when inhs goes to 0 v, csns goes to 5.0 v. in figure 16, page 19 , the out pin is short-circuited to 0 v. when the current reaches i och , out is turned off within t och owing to internal logic circuit. overload fault on low side this fault detection is active when inls is logic [1]. low- side overload protection does not measure the current directly but rather its effects on the low-side mosfet. when table 5. operating modes condition conf inhs inls out gls fs en comments sleep x x x x x h l device is in sleep mode. the out and low-side gate are off. normal l h h h h h h normal mode. high side and low side are controlled independently. the high side and the low side are both on. normal l l l l l h h normal mode. high side and low side are controlled independently. the high side and the low side are both off. normal l l h l h h h normal mode. half-bridge confi guration. the high side is off and the low side is on. normal l h l h l h h normal mode. half-bridge confi guration. the high side is on and the low side is off. normal h pwm h pwm pwm_bar h h normal mode. cross-conducti on management is activated. half-bridge configuration. h = high level l = low level x = don?t care pwm_bar = opposite of pulse -width modulation signal.
analog integrated circuit device data 14 freescale semiconductor 33981 functional device operation protection and di agnostic features v dls > v ocls , the gls pin goes to 0 v and the ocls internal current source is disconnected and ocls goes to 0 v. the gls pin and the ocls pin are reset (and the fault is delatched) by a logic [0] at the inls pin for at least t rst(diag) . figure 13, page 17 and figure 14, page 18 illustrate the behavior in case of overload on low side gate driver. when connected to an external resistor, the ocls pin with its internal current source sets the v ocls level. by changing the external resistance, the pr otection level can be adjusted depending on low-side characteristics. a 33k ? resistor gives a v ds level of 3.3 v typical. this protection circuitry meas ures the voltage between the drain of the low side (dls pin) and the 33981 ground (gnd pin). for this reason it is key that the low-side source, the 33981 ground, and the external resistance ground connection are connec ted together in order to prevent false error detection due to ground shifts. the maximum ocls voltage being 4.0v, a resistor bridge on dls must be used to detect a higher voltage across the low side. configuration the conf pin manages the cross-conduction between the internal mosfet and the external low-side mosfet. with the conf pin at 0 v, the two mosfets can be independently controlled. a load can be placed between the high side and the low side. with the conf pin at 5.0 v, the two mosfets cannot be on at the same time. they are in half-bridge configuration as shown in the simplified application diagram on page 1 . if inhs and inls are at 5.0 v at the same time, inhs has priority and out will be at v pwr . if inhs changes from 5.0 v to 0 v with inls at 5.0 v, gls will go to high state as soon as the v gs of the internal mosfet is lower than 2.0 v typically. a half-bridge application could consist in sending pwm signal to the inhs pin and 5.0 v to the inls pin with the conf pin at 5.0 v. figure 20, page 22 , illustrates the simplified application diagram on page 1 with a dc motor and external low side. the conf and inls pins are at 5.0 v. when inhs is at 5.0 v, current is flowing in the motor. when inhs goes to 0 v, the load current recirculates in the external low side. bootstrap supply bootstrap supply provides current to charge the bootstrap capacitor through the v pwr pin. a short time is required after the application of power to the device to charge the bootstrap capacitor . a typical value for this capacitor is 100 nf. an internal charge pump allows continuous mosfet drive. when the device is in the sleep mode, this bootstrap supply is off to minimize current consumption. high-side gate driver the high-side gate driver sw itches the bootst rap capacitor voltage to the gate of the mo sfet. the driver circuit has a low-impedance drive to ensure that the mosfet remains off in the presence of fast falling dv/dt transients on the out pin. this bootstrap capacitor co nnected between the power supply and the c boot pin provides the h igh pulse current to drive the device. the voltage across this capacitor is limited to about 13 v typical. an external capacitor connected between pins sr and gnd is used to control the slew rate at the out pin. figure 9, page 10 and figure 10, page 11 give vout rise and fall time versus different sr capacitors. low-side gate driver the low-side control circuitry is pwm capable. it can drive a standard mosfet with an r ds(on) as low as 10.0 m ? at a frequency up to 60 khz. the v gs is internally clamped at 12 v typically to protect the gate of the mosfet. the gls pin is protected against short by a local over temperature sensor. thermal feedback the 33981 has an analog feedback output (temp pin) that provides a value in inverse proportion to the temperature of the gnd flag (pin 13). the controlling microcontroller can ?read? the temperature proporti onal voltage with its analog- to- digital converter (adc). this can be used to provide real- time monitoring of the pc board temperature to optimize the motor speed and to protect the whole elec tronic system. temp pin value is v tfeed with a negative temperature coefficient of dt feed . reverse battery the 33981 survives the application of reverse battery voltage as low as -16 v. under these conditions, the output?s gate is enhanced to decrease device power dissipation. no additional passive components are required. the 33981 survives these conditions until the maximum junction rating is reached. in the case of reverse battery in a half-bridge application, a direct current passes through the external freewheeling diode and the internal high-side. as figure 11 shows, it is essential to protect this power line. the proposed solution is an external n-channel low-side with its gate tied to battery voltage through a resistor. a high-side in the v pwr line could be another solution.
analog integrated circuit device data freescale semiconductor 15 33981 functional device operation protection and di agnostic features figure 11. reverse battery protection ground (gnd) disco nnect protection if the dc motor module ground is disconnected from load ground, the device protects itself and safely turns off the output regardless of the out put state at the time of disconnection. a 10k resistor needs to be added between the en pin and the rest of the circuitry in order to ensure the device turns off in case of ground disconnect and to prevent exceeding this pin? s maximum ratings. fault reporting this 33981 indicates the faults below as they occur by driving the fs pin to logic [0]: ? overtemperature fault ? overcurrent fault on out ? overload fault on the external low-side mosfet the fs pin will return to logic [1] when the over temperature fault condition is removed. the two other faults are latched. m v pwr v dd v pwr mcu 33981 no current gnd out diode 10.0 k ? table 6. functional truth table in fault mode conditions conf inhs inls out gls fs en temp csns ocls comments overtemperature on out x x x l h l h l x x the 33981 is currently in fault mode. the out is off. temp at 0 v indicates this fault. once the fault is removed 33981 recovers its normal mode. overtemperature on gls x x x l l l h l x x the 33981 is currently in fault mode. the out is off and gls is at 0 v. temp at 0 v indicates this fault. once the fault is removed 33981 recovers its normal mode. overcurrent on out x h l l x l h x l x the 33981 is currently in fault mode. the out is off. it is reset by a logic [0] at inhs for at least t rst(diag) . when inhs goes to 0 v, csns goes to 5.0 v. overload on external low- side mosfet l l h x l l h x x l the 33981 is currently in fault mode. gls is at 0 v and ocls internal current source is off. the external resistance connected between ocls and gnd pin will pull ocls pin to 0 v. the fault is reset by a logic [0] at inls for at least t rst(diag) . h = high level l = low level x = don?t care
analog integrated circuit device data 16 freescale semiconductor 33981 functional device operation protection and di agnostic features figure 12. overtemperature on output en conf inhs inls out thermal shutdown gls fs temp high side on high side off temperature out tsd tsd hysteresis hysteresis 0.0 v 5.0 v 0.0 v 0.0 v 5.0 v 0.0 v 5.0 v 5.0 v on out thermal shutdown on out
analog integrated circuit device data freescale semiconductor 17 33981 functional device operation protection and di agnostic features figure 13. overload on lo w-side gate drive, case 1 en inls gls fs overload on low side t rst(diag) ocls v ds_ls low side off v ds_ls = v ocls case 1: overload removed 0.0 v 0.0 v 0.0 v 5.0 v 0.0 v 5.0 v 5.0 v
analog integrated circuit device data 18 freescale semiconductor 33981 functional device operation protection and di agnostic features figure 14. overload on lo w-side gate drive, case 2 inls gls fs overload on low side t rst(diag) ocls v ds_ls case 2: low side still overloaded low side off v ds_ls = v ocls 0.0 v 0.0 v 0.0 v 0.0 v en 5.0 v
analog integrated circuit device data freescale semiconductor 19 33981 functional device operation protection and di agnostic features figure 15. overcurrent on output figure 16. high-side overcurrent inhs out fs t rst(diag) csns i out i och fault removed overcurrent on high side 0.0 v 0.0 v 0.0 v vcl (csns) 0.0 v 5.0 v en 5.0 v
analog integrated circuit device data 20 freescale semiconductor 33981 functional device operation protection and di agnostic features figure 17. cross-conduction with low side figure 18. overtemperature on out recirculation in low side current in motor overtemperature temp inhs out i out
analog integrated circuit device data freescale semiconductor 21 33981 functional device operation protection and di agnostic features figure 19. maximum operating frequency for sr capacitor of 4.7 nf
analog integrated circuit device data 22 freescale semiconductor 33981 typical applications introduction typical applications introduction figure 20 shows a typical application for the 33981. a brush dc motor is connected to th e output. a low-side gate driver is used for the freewheeling phase. typical values for external capacitors and resistors are given. . figure 20. 33981 typical application diagram emc and emi recommendations introduction this section relates the emc capability for 33981, high frequency high-current high-side switch. this device is a self-protected silicon switch used to replace electromechanical relays, fuses, and discrete circuits in power management applications. this section presents the key fe atures of the device and its targeted applications. the automotive standard to measure conducted and radiated emissions is provided. concrete measurements on the 33981 and improvements to reduce electromagnetic emission are described. device features this 33981 is a 4.0 m ? self-protected, high-side switch digitally controlled from a microcontroller (mcu) with extended diagnostics, able to drive dc motors up to 60 khz. a bootstrap architecture has been used to provide fast transient gate voltage in order to reach 4.0 m ? r ds(on) maximum at room temperature. in parallel, a charge pump is implemented to offer continu ous on-state capability. this dual current supply of the high-side mosfet allows a duty cycle from 5% to 100%. an external capacitor connected between pins sr and gnd is used to control the slew rate at the output and, ther efore, reduce electromagnetic perturbations. in standard configuration, the motor current recirculation is handled by an external freewheeling diode. to reduce global power dissipation, the freewheeling diode can be replaced by an external discrete mosfet in low-side configuration. the ic integrates a gate driver t hat controls and protects this external mosfet in the event of short circuit to battery. the product manages the cross c onduction between the internal high side and the external low side when used in a half bridge configuration. the two mosfets can be controlled independently when the conf pin is at 0 v. to eliminates fuses, the device is self-protect ed from severe short-circuits (100 a typical) with an innov ative overcurrent strategy. the 33981 has a current feedback for real-time monitoring of the load current through an mcu analog/digital converter to facilitate closed-loop operation for motor speed control. the 33981 has an analog thermal feedback that can be used by the mcu to monito r pc board temperature to optimize the motor control and to protect the entire electronic system. therefore, an over temperature s hutdown feature protects the ic against high overload condition. mcu 33981 out sr en fs inhs csns i/o i/o i/o a/d gnd vpwr v dd cboot gls inls i/o dls temp a/d conf ocls v pwr v dd m 2.2 nf 1.0 k ? 1.0 k ? 33 k ? 330 f 100 nf 100 nf 10 k ? 10 k ? 10 k ? 10 k ? voltage regulator v pwr
analog integrated circuit device data freescale semiconductor 23 33981 typical applications emc and emi recommendations figure 21 illustrates the typical application diagram. figure 21. typical application diagram application engine cooling, air conditioning, and fuel pump are the targeted automotive applicati ons for the 33981. conventional solutions are designed with discrete components that are not optimized in terms of compon ent board size, protection, and diagnostics. the 33981 is the right candidate to develop lighter and more compact units. dc motor speed adjustment allo ws optimization of energy consumption by reducing suppl y voltage, hence the mean voltage, applied to the motor. the commonly used control technique is pulse wide modulation (pwm) where the average voltage is proportiona l to the duty cycle. most applications require a pwm frequency of at least 20 khz to avoid audible noise. figure 22 illustrates typical waveforms when switching the 33981 at 20 khz with a duty cycle of 80%. the output voltage (out) and current in the motor (i motor ) waveforms are represented. figure 22. current and voltage waveforms how to measure electromagnetic emission according to the cispr25 one emc standard in the automotive world (at system level) is the cispr25, edited by the international electrotechnical commission. th is standard describes the measurement method to measure both conducted and radiated emission. conducted emission measurement conducted emission is the emission produced by the device on the battery cable. th e test bench is described by cispr25 (see figure 23, test bench for conducted emission , on page 23 ). the line impedance stabilization network (lisn), also called artificial network (an), in a given frequency range (150 khz to 108 mhz) provides a specified load impedance for the measurement of disturban ce voltages and isolates the equipment under test (eut) from the supply in that frequency range. figure 23. test bench for conducted emission the eut must operate under typical loading and other conditions just as it must in the vehicle so maximum emission state occurs. these operating c onditions must be clearly defined in the test plan to ensure that both supplier and customer are performing identical tests. for the testing described in this application note, the out pin of the 33981 was connected to an inductive load (0.47 ? + 1.0 mh) switching at 20 khz with a duty cycle of 80%. the output current was 17 a continuous. the ground return of the eut to the chassis must be as short as possible. the power supply is 13.5 v. radiated emission measurement the radiated emission measurement consists of measuring the electromagnetic radiation produced by the equipment under test. cispr 25 gives the schematic test bench described in figure 24, test bench for radiated emission , on page 24 . to measure radiated emission over all frequency ranges, several antenna types must be used: ? 0.15 mhz to 30 mhz: 1.0 m vertical monopole in vertical polarization. ? 30 mhz to 200 mhz: a biconical antenna used in vertical and horizontal polarization. ? 200 mhz to 1,000 mhz: a log-periodic antenna used in vertical and horizontal polarization. imotor (10a/div) out mc33981 on mc33981 off load bf generator lisn spectrum analyzer eut out ground contact to ground plane + - ground plane in copper su pp l y m m 200 0 200 + coaxial cable electrical to optical converter high side driver signal 12v power supply power supply non-conductive material
analog integrated circuit device data 24 freescale semiconductor 33981 typical applications emc and emi recommendations figure 24. test bench for radiated emission emc results an d improvements the 33981 out is connected to an inductive load (0.47 ? + 1.0 mh) switching at 20 khz with duty = 80%. the current in the load was 17 a continuous. board setup the initial configuration of our 33981 board is represented in figure 25 . no sr capacitor is used. therefore, the obtained switching times are the maxi mum values. a capacitor of 1000 mf is connected between vpwr and gnd. figure 25. 33981 initial configuration conducted measurements test setup to perform a conducted em ission measurement in accordance with the cispr 25 standard, the test bench in figure 26, conducted emission test setup , on page 24 was developed. figure 26. conducted emission test setup effects of some parameters the conducted emissions level rise with the duty cycle. when the duty increases the di/dt on the vpwr line is higher. the device has to deliver more current and provide more energy. figure 27 describes the effect of duty cycle increase on the v pwr current waveform. the conducted emission level rises with the output fr equency. this is due to the increasing number of commutations. key 1 eut (grounded locally if required in test plan) 8 biconical antenna 2 test harness ? ? 3 load simulator (placement and ground connection) 10 high quality double- shielded coaxial cable (50 ? ) 4 power supply (location optional) 11 bulkhead connector 5 artificial network (an) 12 measuring instrument 6 ground plane (bonded to shielded enclosure) 13 rf absorber material 7 low relative permittivity support ( ? 1.4) 14 stimulation and monitoring system out gnd v pwr 33981 power supply lisn measurement point for conducted emission eut non-conductive material optical pwm signal load (1.0 mh + 0.47 ? )
analog integrated circuit device data freescale semiconductor 25 33981 typical applications emc and emi recommendations figure 27. vpwr current how to reduce electromagnetic emission by adjusting the slew rate of the device during turn on and turn off with sr capacitor, the electromagnetic emissions can be reduced. conductive emission tests were performed (taking care of the board filtering and routing that have a big impact on emc performances). an optimized solution was found by adding the following external components to the initial board: ? pi filter on the v pwr : 2 x 3 mf and 3.5 uh ? rc in filter between v pwr and gnd: a 2.0 ? resistor in series with a 100 nf capacitor ? rc out filter between out and gnd: a 4.7 ? resistor in series with a 100 nf capacitor ? capacitor c1 of 10 nf between v pwr and gnd ? capacitor c2 of 10 nf between out and gnd ? capacitor c3 of 10 nf between out and v pwr ? capacitor sr of 3.3 nf figure 28. 33981 with filter the emc enhanced board with adapted value filter is represented in figure 29, enhanced board , on page 25 . figure 29. enhanced board the chart in figure 30 shows the spectrum of the enhanced board and the initial board. the improvement is appreciatively 15 db to 20 db in the all frequency range. the enhanced board is now in accordance with the class 3 limits of the cispr25 standard for conducted emission. figure 30. conducted emission spectrum for 33981 radiated measurements this test was performed in order to evaluate the characteristic of the device relating to radiated emission. measurements have been done in accordance with the di/dt di/dt duty cycle increase i(t) on v bat t 33891 100 nf 2 ? c1 = 10 nf sr 3.3 nf 100 nf 4.7 ? pi filter c3 = 10 nf c2 = 10 nf 3000 f 3.5 h inductive load free wheel diode out v bat rc in filter rc out filter gnd 33981 pi filter c3 c1 sr rc out filter c2 rc in filter
analog integrated circuit device data 26 freescale semiconductor 33981 typical applications power dissipation cispr 25 standard as shown in figure 31 . the tested board was the emc enhanced board. figure 31. radiated emission test set up the results of these measur ements are represented in figure 32 . the enhanced board is in accordance with the class 3 limits of the cispr25 standard for radiated emission. figure 32. radiated emission spectrum for 33981 conclusion this document explains how to measure conducted and radiated emission in accordance with the automotive cispr25 standard. measurement s were performed on the 33981 in real application conditi ons when driving an inductive load. an optimized filtering solution was put in place to have the tested system in accordance with the class 3 limits. the same method can be used with other pc boards. power dissipation introduction this section relates to the power dissipation capability for 33981, high frequency high-current high-side switch. this device is a self-protected silicon switch used to replace electromechanical relays, fuses, and discrete circuits in power management applications. this section presents the key fe atures of the device and its targeted applications. the theoretical calculations for power dissipation and die junction tem peratures are determined in this document for inductive loads. a concrete example with dc motor driven by the 33981 is analyzed in section dc motor 200 w. device features this 33981 is a 4.0 m ? self-protected, high-side switch digitally controlled from a microcontroller (mcu) with extended diagnostics, able to drive dc motors up to 60 khz. a bootstrap architecture has been used to provide fast transient gate voltage in order to reach 4.0 m ? r ds(on) maximum at room temperature. in parallel, a charge pump is implemented to offer continu ous on-state capability. this dual current supply of the high-side mosfet allows a duty cycle from 5% to 100%. an external capacitor connected between pins sr and gnd is used to control the slew rate at the output and, ther efore, reduce electromagnetic perturbations. in standard configuration, the motor current recirculation is handled by an external freewheeling diode. to reduce global power dissipation, the freewheeling diode can be replaced by an external discrete mosfet in low-side configuration. the ic integrates a gate driver t hat controls and protects this external mosfet in the event of short circuit to battery. the product manages the cross c onduction between the internal high side and the external low side when used in a half bridge configuration. the two mosfets can be controlled independently when the conf pin is at 0 v. to eliminates fuses, the device is self-protect ed from severe short-circuits (100 a typical) with an innov ative overcurrent strategy. the 33981 has a current feedback for real-time monitoring of the load current through an mcu analog/digital converter to facilitate closed-loop operation for motor speed control. the 33981 has an analog thermal feedback that can be used by the mcu to monito r pc board temperature to optimize the motor control and to protect the entire electronic system. therefore, an over temperature s hutdown feature protects the ic against high overload condition. 1.5 m length of cable lisn and inductive load 1 m vertical monopole antenna anechoic chamber eut cispr class 3 limits 33981 emission
analog integrated circuit device data freescale semiconductor 27 33981 typical applications power dissipation figure 33 illustrates the typical application diagram. figure 33. typical application diagram application engine cooling, air conditioning, and fuel pump are the targeted automotive applicati ons for the 33981. conventional solutions are designed with discrete components that are not optimized in terms of compon ent board size, protection, and diagnostics. the 33981 is the right candidate to develop lighter and more compact units. the adjustment of the dc motor speed allows optimizing of energy consumption. it is real ized by chopping the supply voltage, hence the mean voltage, applied to the motor. the commonly used control technique is pulse wide modulation (pwm) where the average voltage is proportional to the duty cycle. most applications require a pwm frequency of at least 20 khz to avoid audible noise. figure 34 illustrates typical waveforms when switching the 33981 at 20 khz with a duty cycle of 80%. the output voltage (out) and current in the motor (i motor ) waveforms are represented. figure 34. current and voltage waveforms power dissipation the 33981 power dissipation is the sum of two kinds of losses: ? on-state losses when device is fully on, ? switching losses when the device switches on and off. the analysis that follows assumes an inductive load and assumes that the current is constant in the load. the case being considered in this paper is inductive load and the hypothesis is that the cu rrent is constant in the load. on-state losses the mean on-state loss periods in the 33981 can be calculated as follows: pon_state = a r ds(on) i out 2 where ?a? is the duty cycle. the critical parameter is the on resistance (r ds(on) ) that increases with temperature. the 33981 has a maximum r ds(on) at 25oc of 4.0 m ? and its deviation with temperature is only 1.7 as shown in figure 35 . figure 35. r ds(on) vs. temperature switching losses the mean switching losses in the 33981 can be calculated as follows: pswitching = (t on . f req . v pwr . i out ) / 2 + (t off . f req . v pwr . i out ) / 2 where t on /t off is the turn on/off time. the switching time is a critical parameter. the 33981 provides adjustable slew rates through an external capacitor (sr) that slow down the rise and fall times to reduce the electromagnetic emissions. ho wever, this adjustment will have an impact on power dissipation. figure 36 gives the positive (sr r ) and negative (sr f ) slew rate versus different values of sr. this is illustrated in figure 37 . imotor (10a/div) out mc33981 on mc33981 off 0 1 2 3 4 5 6 7 -50 0 50 100 150 200 temperature (c) r dson (mohm)
analog integrated circuit device data 28 freescale semiconductor 33981 typical applications power dissipation figure 36. positive and negative slew rate vs. sr capacitor figure 37. out switching vs. sr capacitor junction temperature the junction temperature of the 33981 can be calculated knowing the power dissipation and the thermal characteristics of the pc board with this formula: t j = t a + (pon_state + pswitching). r thja where t j is the junction temperature, t a the ambient temperature, and r thja the thermal impedance junction to ambient. recirculation phase in standard configuration, the motor current recirculation is handled by an external freewheeling diode. with the 33981, the freewheeling diode can be replaced by an external low- side discrete mosfet. the power dissipation during the recirculation phase is calculated as follows for the diode and the low-side mosfet respectively: pdiode = (1-a) . v f . i out where ?a? is the duty cycle pmosfet_ls = (1-a) . r ds(on)_ls . i out 2 where r ds(on)_ls is the on resistance of the low side. applications examples excel tool an excel tool has been created with all the above formulas to calculate the dissipated power and the junction temperature knowing the application conditions. an example of the interface is given in figure 38 . the parameters to enter concern the load, the high-side device, the recirculation, and the board. they are v pwr , dc current in the load (imax for 100% of duty cycle), pwm frequency, 33981 r ds(on) at 150oc, sr capacitor, low-side r ds(on) at 150oc, ambient temperature, and thermal impedance. figure 38. excel tool the calculations are done with the maximum r ds(on) for the 33981 and the low side. the current is also considered constant in the load. the model taken for the v f of the diode is (0.4 + 0.01 . i out ) volts. the listed conditions in figure 38 are the ones chosen for the entire document. 0 20 40 60 80 100 120 4.56 91427 vbat srr(v/s) 0 1 2.2 3.3 4.7 6.8 0 10 20 30 40 50 60 70 80 90 4.5 6 9 14 27 vbat srf(v/s) 0 1 2.2 3.3 4.7 6.8 vpwr 12 v imax 20 a frequency 20 khz r dson @150c 6.8 mohm sr capacitor 0 nf r dson @150c 20 mohm rthja 15 c/w t ambiant 85 c inputs low side characteristics high side device (hs) load recirculation board
analog integrated circuit device data freescale semiconductor 29 33981 typical applications power dissipation dc motor 200 w a concrete example is the 33981. a 200 w dc motor, a frequency of 20 khz, and an ambient temperature of 85oc are chosen. the 33981 is evaluated using the following board. the thermal impedance of the board is in the range of 15oc/w. figure 39. 33981 evaluation board power dissipation figure 40 illustrates the power dissipation in the 33981. the conditions are listed in figure 38 . maximum power dissipation of 3.1 w is obtained with a duty of 95%. figure 40. power dissipation (pon and pswitching) vs. duty cycle influence of sr capacitor the sr capacitor value has an impact on these switching losses. figure 41 illustrates the percentage of the switching losses versus the total power dissipation for the same load conditions as figure 38 . the higher the sr capacitor value, the higher the switching losses. they can be more than 50% of the total power dissipation in the 33981 with a 4.7 nf capacitor and is a basic applications trade-off. a compromise should be found between the power dissipation and the electromagnetic capability (emc) performance. figure 41. power swit ching vs. sr capacitor recirculation phase figure 42 illustrates the power dissipation for the two recirculation approaches, diode or low-side mosfet. the power dissipation gai n for the entire system when using the low side instead of the diode can reach up to 1.5 w with a duty cycle of 50%. figure 42. total board power dissipation junction temperature the junction temperature of the 33981 versus duty cycle for the condition listed in figure 38 , is given in figure 43 . the maximum obtained junction temperature is 132oc with a duty 0 0.5 1.5 2.5 3.5 0 10 20 30 40 50 60 70 80 90 100 pon_state p switching ptotal mc33981 power dissipation 3.0 2.0 1.0 duty cycle (%) mc33981 power dissipation (w) 0 1 2 3 4 5 6 02.23.34.7 pswitching pon csr (nf) power dissipation (w) 0 1 2 3 4 5 6 02.23.34.7 pswitching pon csr (nf) power dissipation (w) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 50 60 70 80 90 100 power hs power diode power total board with diode power ls power total board with ls total board power dissipation power dissipation (w) ratio pwm %
analog integrated circuit device data 30 freescale semiconductor 33981 typical applications power dissipation cycle of 95%. this value is far from the 150oc maximum guaranteed junction. figure 43. junction temperature vs. duty cycle conclusion knowing the application c onditions, this document explained how to calculate power dissipation during on-state and switching phases and the junction temperature for the 33981 when controlling a dc motor. a concrete example with a 200 w dc motor was given in section dc motor 200 w. the same principle can be used for other dc motor and other environmental conditions. 0.00 20.00 40.00 60.00 80.00 100.00 120.00 140.00 0 10 20 30 40 50 60 70 80 90 100 duty cycle (%) junction temperature (c)
analog integrated circuit device data freescale semiconductor 31 33981 packaging soldering information packaging soldering information the 33981 is not designed for immersion soldering. the maximu m peak temperature during the soldering process should not exceed 245 o c. pin soldering limit is for 10 seconds maximum dura tion. exceeding these limits may cause malfunction or permanent damage to the device. packaging dimensions for the most current pa ckage revision, visit www.freescale.com and perform a keyword search using ?98arl10521d?. pna suffix 16-pin pqfn plastic package 98arl10521d issue c
analog integrated circuit device data 32 freescale semiconductor 33981 packaging packaging dimensions pna suffix 16-pin pqfn plastic package 98arl10521d issue c
analog integrated circuit device data freescale semiconductor 33 33981 additional documentation thermal addendum (rev 2.0) additional documentation thermal addendum (rev 2.0) introduction this thermal addendum is provided as a supplement to the 33981 technical datasheet. the addendum pr ovides thermal performance information that may be critical in the design and development of system appl ications. all electrical, application, and packaging information is provided in the datasheet. packaging and thermal considerations this package is a dual die package. ther e are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r jamn . for m , n = 1, r ja11 is the thermal resistance from junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m = 1, n = 2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22, respectively. the stated values are solely for a thermal performance comparison of one package to another in a standard ized environment. this methodology is not meant to and will not predict the perfor mance of a package in an applic ation-specific environment. stat ed values were obtained by measurement and simula tion according to the standards listed below. standards figure 44. surface mount for power pqfn with exposed pads 16-pin pqfn 33981 pna suffix 98arl10521d 16-pin pqfn 12 mm x 12 mm note for package dimensions, refer to the 33981 device datasheet. t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 table 7. thermal performance comparison thermal resistance 1 = power chip, 2 = logic chip [ c/w] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 ja mn (1) , (2) 22 18 41 jb mn (2) , (3) 7.0 4.0 27 ja mn (1) , (4) 62 48 81 jc mn (5) <1.0 0.0 1.0 notes 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad, ?infinite? heat sink attached to exposed pad. 0.2 mm spacing between pcb pads note: recommended via diameter is 0.5 mm. pth (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via. 0.2 mm spacing between pcb pads
analog integrated circuit device data 34 freescale semiconductor 33981 additional documentation thermal addendum (rev 2.0) figure 45. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air . this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the junction temperature is sensed. 16-pin pqfn 0.90 mm pitch 12.0 mm x 12.0 mm body 33981 pin connections transparent top view a with exposed pads 1 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 out out csns temp en inhs fs inls conf ocls dls gls sr cboot gnd vpwr material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a: cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 8. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( c/w) m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 ja mn 066 51 84 300 47 37 73 600 43 34 70
analog integrated circuit device data freescale semiconductor 35 33981 additional documentation thermal addendum (rev 2.0) figure 46. device on thermal test board r ja figure 47. transient thermal resistance r ja , 1w step response,device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 70 80 90 heat spreading area a [m m 2] thermal resistance [oc/w] 0 300 600 r ja11 r ja22 r ja12 =r ja21 x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] r ja11 r ja22 r ja12 =r ja21 x
analog integrated circuit device data 36 freescale semiconductor 33981 revision history revision history revision date description of changes 3.0 1/2006 ? implemented revision history page ? made content updates and changes ? converted to freescale format ? added thermal addendum 4.0 3/2006 ? made minor content changes to pages 6 and 7. ? updated to product preview status 5.0 7/2006 ? changed part number from pc33981pna to mc33981Bpna (page 1 ) ? changed electrical characteristics, maximum ratings, table 2, maximum ratings, electrical ratings, ocls voltage, from ?-5.0 to 5.0? to ?-5.0 to 7.0? (page 4 ). ? changed electrical characteristics, static el ectrical characteristics, table 3, static electrical characteristics, low side gate driver (vpwr, vgls, vocls), low-side overload detection level versus low-side dr ain voltage minimum, from ?-75? to ?-50? and maximum from ?+75? to ?+50? (page 6 ). ? changed electrical characteristics, dynami c electrical characteristics, table 4, dynamic electrical characteristics, control interface and power output timing (cboot, vpwr), input switching frequency, minimum from ?20? to ?-? and typical from ?-? to ?20? (page 7 ). ? updated to advanced status 6.0 5/2007 ? changed csns input clamp current in maximum ratings ? changed figure 11, reverse battery protection ? removed unnecessary line in figure 14, overload on low-side gate drive, case 2 ? corrected label in figure 28, 33981 with filter
mc33981 rev. 6.0 5/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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